fpga engineer.

job summary: An Optical Engineer is needed for an American social media conglomerate corporation in the Sunnyvale, CA area. This position will have hands-on experiences with lab equipments and familiar with camera test methodologies. Candidate should have Bachelor's degree in the field of Optical Sciences, Physics, Electrical Engineering, Computer Science, Image Processing or a related technical discipline.   location: Sunnyvale, California job type: Contract salary: $63.33 - 95.33 per hour work hours: 8am to 5pm education: Bachelors   responsibilities: Collaborate with opto-ME, EE, and optics teams to design, build and bringup lab setups for image data acquisition of camera prototypes to support camera design studies.Develop and document camera test methodologies to support 2D/3D camera system performance analysis.Develop and debug test scripts for image data collection automation.Processing, analysis and organizing measurement data, presentation of initial analysis.Drive supplier interaction and management in order to deliver camera prototypes in support of concept demonstrations.Operate, calibrate and perform routine maintenance of lab equipments. Skills: Familiar with image sensor, imaging optics, and image processing algorithms.Ability to work with minimal direction and managing a project independently from start to finish.Working, communicating, and collaborating in a cross-functional team environment. Education/Experience: Bachelor's degree in the field of Optical Sciences, Physics, Electrical Engineering, Computer Science, Image Processing or a related technical discipline.Experiences in image quality testing of camera systems and familiar with image quality metrics.Hands on experience in the development of opto-mechanical lab setups for camera system performance study; familiar with optical metrology.Experiences in Python, Matlab or other scripting software for automated image capture.Experiences with image data processing and analysis 11284-1.Experiences in camera calibration and modeling of imaging systems.Experiences in documentation of camera test procedure and methodologies.   qualifications: Experience level: ExperiencedEducation: Bachelors  skills: OpticsPythonMatlab3DAutomation Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status. At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com. Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance. We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance. For certain assignments, Covid-19 vaccination and/or testing may be required by Randstad's client or applicable federal mandate, subject to approved medical or religious accommodations. Carefully review the job posting for details on vaccine/testing requirements or ask your Randstad representative for more information

job summary: A Silicon DV Engineer is needed for an American social media conglomerate corporation. Remote work. This position wil define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.   location: Remote, Remote job type: Contract salary: $84.00 - 126.19 per hour work hours: 8am to 5pm education: Bachelors   responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design qualityDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry Minimum qualifications: Track record of 'first-pass success' in ASIC development cyclesHands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodologyExperience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologiesExperience in one or more of the following areas along with functional verification - SV Assertions, Formal, EmulationExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Preferred qualifications: Experience in development of UVM based verification environments from scratchExperience with Design verification of pipeline designsExperience with revision control systems like GitExperience with verification of ARM/RISC-V based sub-systems or SoCsExperience with IP or integration verification of high-speed interfaces like PCIe, DDR, EthernetExperience working across and building relationships with cross-functional design, model and emulation teams   qualifications: Experience level: ExperiencedEducation: Bachelors  skills: Design EngineerSystemVerilogPipingASIC/FPGA/PLD Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status. Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance. We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance. For certain assignments, Covid-19 vaccination and/or testing may be required by Randstad's client or applicable federal mandate, subject to approved medical or religious accommodations. Carefully review the job posting for details on vaccine/testing requirements or ask your Randstad representative for more information.

job summary: A Silicon DD Engineer is needed for an American social media conglomerate corporation in the Sunnyvale, CA area. This position will contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification. Candidate should have 4+ years of experience as a Digital Design Engineer and/or a Chip Lead.   location: Sunnyvale, California job type: Contract salary: $66.67 - 100.47 per hour work hours: 8am to 5pm education: Bachelors   responsibilities: Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verificationIPs integrationUnderstand Design for Verification conceptsDrive the top-level µArchitecture definition and develop the necessary RTLDrive the chip-level integration, verification plan development and verificationSupervise the RTL-to-GDS flow and assist with synthesis and timing closureSupport the test program development, chip validation and chip life until production maturityWork with FPGA engineers to perform early prototypingSupport hand-off and integration of blocks into larger SOC environmentsAssist with Algorithm analysis, verification and improvementContribute to ASIC digital architecture, design and verification Skills: Must Have: 4+ years of experience as a Digital Design Engineer and/or a Chip LeadExperience in RTL coding, synthesis and/or SoC IntegrationExperience in digital design µArchitectureBS Electrical Engineering/Computer Science or equivalent experienceExperience with UPF based simulation flowSystem Verilog OVM/UVM experienceTcl and Python (or similar) scripting experienceExperience in SoC integration and ASIC architecture Wish List/ Nice to Have: Experience in DFT/Testability requirement and test program definitionExperience using High Speed interfaces like PCIe, USB, MIPIFPGA designTensilica DSP, TIE, CNN, fixed point, floating point, python.Experience with Power Aware GLS flowMSEE/CS or equivalent experience Education: Must Have: Bachelor degree in Electrical/Computer Engineering or Computer ScienceMaster's Degree preferred but not required   qualifications: Experience level: ExperiencedEducation: Bachelors  skills: Digital Design EngineerASIC/FPGA/PLD Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status. Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance. We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance. For certain assignments, Covid-19 vaccination and/or testing may be required by Randstad's client or applicable federal mandate, subject to approved medical or religious accommodations. Carefully review the job posting for details on vaccine/testing requirements or ask your Randstad representative for more information.