Responsibilities:
- The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.
- Expertise with debugging in Best/Worst SDF with min/max corner simulations.
- Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.
- Experience with timing constraints and multi clock domain design
- Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
- Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverage
- Work as a team to grow together.
- Mentor and coach junior team members
- Power-Aware simulation experience is desirable.
location: San Jose, California
job type: Contract
salary: $75 - 85 per hour
work hours: 8am to 5pm
education: No Degree Required
responsibilities:
Responsibilities:
- The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.
- Expertise with debugging in Best/Worst SDF with min/max corner simulations.
- Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.
- Experience with timing constraints and multi clock domain design
- Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
- Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverage
- Work as a team to grow together. Mentor and coach junior team members
- Power-Aware simulation experience is desirable.
qualifications:
- Experience level: Experienced
- Minimum 7 years of experience
- Education: No Degree Required
skills:
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