Exciting tech company is seeking a Hardware Engineer IV for their hardware team. This engineer will be working on an exciting new project while also designing optimized TIE floating point modules and TIE operations, conduct full verification (ISS and RTL) of the TIE modules and operations, RTL module design and design/Verify other TIE operations. The ideal candidate has a minimum 5 years of RTL design experiences using industry standard EDA tools, ability to write basic C codes to conduct RTL/TIE design verification,
strong knowledge of IEEE floating point specifications and previous experience in Tensilica TIE design.
location: Menlo Park, California
job type: Contract
salary: $75 - 110 per hour
work hours: 7am to 3pm
- Design optimized TIE floating point modules and TIE operations for Tensilica DSP.
- Area and Energy optimized
- Conduct full verification (ISS and RTL) of the TIE modules and operations
- Document the usage of the developed modules and operations
- Design/Verify other TIE operations (non floating-point) for FCV DSP
- Design RTL modules for DSP integration into FCV system
- RTL module design
- RTL module verification (functional and timing)
qualifications: Preferred qualifications:
Previous experience in Tensilica TIE design
Knowledge of System C modeling
Experience in Synopsys EDA tools
5+ years of Verilog RTL design & verification experiences, preferably DSP and CPU.
IEEE floating point Verilog RTL design, mathematic execution units of base arithmetic, square root and others Minimum Qualifications:
Strong knowledge of IEEE floating point specifications
Strong experience in floating-point RTL design
Minimum 5 years of RTL design experiences using industry standard EDA tools
Ability to write basic C codes to conduct RTL/TIE design verification Education:
Bachelors in Electrical Engineering or Computer Science
DECISION SUPPORT PANEL
Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.
Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.
We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance.