A Design Verification Engineer is needed for an American social media conglomerate corporation in the Austin, TX area. Design verification engineer with considerable CPU knowledge. Participate in defining UVM infrastructure for the entire family of core IPs. Location:
Austin (preferred), Redmond, Menlo are acceptable alternatives
location: Austin, Texas
job type: Contract
salary: $38.66 - 59.19 per hour
work hours: 8am to 5pm
- Capable of rapidly deploying UVM environments from clean sheet.
- Equally capable at pre-silicon verification as well as in post-silicon / emulation.
- Work with designer to transition any unit-level work from design to verification.
- Should possess strong interpersonal skills and be capable of solving technical conflicts in a constructive manner.
Nice to haves:
- CPU verification experience
- SystemVerilog, Python
- ARMv7, ARMv8, RISC-V experience
- VPI / DPI experience
- Formal tools and techniques
- Performance verification
- BSEE, BCSE, BSCE or higher
- Some industry experience mandatory (internship exp. if recently graduated)
- Experience level: Experienced
- Education: Bachelors (required)
- Design Engineer
- Electrical Engineering
- Design Verification
Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.