Analog Mask Designer

  • location: Chandler, AZ
  • type: Contract
  • salary: $45 - $50 per hour
easy apply

job description

Analog Mask Designer

job summary:
We have a 2 month contract opportunity for an Analog Mask Designer in Chandler, AZ. This project will be completed and the contract will end on 12/21/18.

Job Description:

In this position you must be able to perform a variety of technical and non-repetitive tasks associated with all phases of chip Iayout development, up to and including Unit and Chip-Level Iayout mask design. Must possess strong Iayout design skills, particularly in analog RF (Radio Frequency) design methods and concepts and can develop and maintain Iayout schedules.

 
location: Chandler, Arizona
job type: Contract
salary: $45 - 50 per hour
work hours: 8am to 5pm
education: Associates
 
responsibilities:
Skillsets required, not limited to the following:

8+ years of directly related experience

Must be able to plan, draw, assemble and verify highly complex Fubs or units

Ability to utilize and follow physical and electrical design rules

The candidate must be knowledgeable and have experience using the Cadence editor and Calibre verification DRC/LVS

Must have experience with TSMC 16FF technology

Technology TSMC (Taiwanese Semiconductor manufacture corporation) 16FF hands-on experience

Proven skills on Analog RF (Radio frequency) circuits/layout

Proven leadership for layout ownership, being self-driver

Experience with layout, including but not limited to: LNA,(Low Noise Amplifier) Regulator, Mixer, bias, Rx blocks, Tx blocks, PA, (Power Amplifier) PLL(Phase lock loop) circuits

Tools: Cadence Virtuoso XL, Calibre LVS/DRC

Experience completing layout top-level and block level

All verification flows: DRC, LVS, antenna, density, latchup, ERC

Generally all required flows for tapeout

Minimum Education requirement: AS - Technical degree and 8+ years of directly related experience

Preferred Skills:

- Experience with extraction and analyzing results: QRC, ASSURA

- Experience with EM and IR-drop analysis

 
qualifications:
Skillsets required, not limited to the following:

8+ years of directly related experience

Must be able to plan, draw, assemble and verify highly complex Fubs or units

Ability to utilize and follow physical and electrical design rules

The candidate must be knowledgeable and have experience using the Cadence editor and Calibre verification DRC/LVS

Must have experience with TSMC 16FF technology

Technology TSMC (Taiwanese Semiconductor manufacture corporation) 16FF hands-on experience

Proven skills on Analog RF (Radio frequency) circuits/layout

Proven leadership for layout ownership, being self-driver

Experience with layout, including but not limited to: LNA,(Low Noise Amplifier) Regulator, Mixer, bias, Rx blocks, Tx blocks, PA, (Power Amplifier) PLL(Phase lock loop) circuits

Tools: Cadence Virtuoso XL, Calibre LVS/DRC

Experience completing layout top-level and block level

All verification flows: DRC, LVS, antenna, density, latchup, ERC

Generally all required flows for tapeout

Minimum Education requirement: AS - Technical degree and 8+ years of directly related experience

Preferred Skills:

- Experience with extraction and analyzing results: QRC, ASSURA

- Experience with EM and IR-drop analysis

 
skills: Skillsets required, not limited to the following:

8+ years of directly related experience

Must be able to plan, draw, assemble and verify highly complex Fubs or units

Ability to utilize and follow physical and electrical design rules

The candidate must be knowledgeable and have experience using the Cadence editor and Calibre verification DRC/LVS

Must have experience with TSMC 16FF technology

Technology TSMC (Taiwanese Semiconductor manufacture corporation) 16FF hands-on experience

Proven skills on Analog RF (Radio frequency) circuits/layout

Proven leadership for layout ownership, being self-driver

Experience with layout, including but not limited to: LNA,(Low Noise Amplifier) Regulator, Mixer, bias, Rx blocks, Tx blocks, PA, (Power Amplifier) PLL(Phase lock loop) circuits

Tools: Cadence Virtuoso XL, Calibre LVS/DRC

Experience completing layout top-level and block level

All verification flows: DRC, LVS, antenna, density, latchup, ERC

Generally all required flows for tapeout

Minimum Education requirement: AS - Technical degree and 8+ years of directly related experience

Preferred Skills:

- Experience with extraction and analyzing results: QRC, ASSURA

- Experience with EM and IR-drop analysis


Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

easy apply

get jobs in your inbox.

sign up
{{returnMsg}}

related jobs


    Software Engineer

  • location: Chandler, AZ
  • job type: Contract
  • salary: $40 - $45 per hour
  • date posted: 9/28/2018