MAC - Verification engineer

  • location: Santa Clara, CA
  • type: Contract
  • salary: $55 - $65 per hour
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job description

MAC - Verification engineer

job summary:
We are looking for an individual to fill a position for a MAC (Media Access Controls) - Verification engineer for a 6+ month project in Santa Clara, CA.

Candidates must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements. The person in this position will also have the following responsibilities: Develop tests and test bench components from high Ievel - Verification plans, as well as debug of failing tests, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space, regression running and debugging failing tests, design and development of test bench collateral. Team members will also work closely with design and architecture teams to review and refine test and coverage requirements.

 
location: Santa Clara, California
job type: Contract
salary: $55 - 65 per hour
work hours: 8am to 5pm
education: Bachelors
 
responsibilities:
Candidates must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements. The person in this position will also have the following responsibilities: Develop tests and test bench components from high Ievel - Verification plans, as well as debug of failing tests, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space, regression running and debugging failing tests, design and development of test bench collateral. Team members will also work closely with design and architecture teams to review and refine test and coverage requirements.

 
qualifications:
Skill sets/Qualifications not limited to the following:

- Minimum 8 years' experience in RTL design verification with SystemVerilog and UVM

- Knowledge and understanding of networking protocols, layer 2 and layer 3

- Knowledge and understanding of high speed Ethernet protocols (25G/50G/100G/400G), including MAC and PCS layers; in-depth knowledge of FEC, scramble/descramble and lane alignment techniques preferred

- Strong Knowledge of possible Serdes and MAC related errors

- Strong logical and problem solving skills

- Experience in Synopsys Ethernet VIP preferred

-Strong debug abilities, good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones

Preferred Skills

-A strong background specifying and developing random test environments is desired.

Minimum Educational requirements: BSEE/CE minimum, MS preferred

 
skills: Team Player, Great Communicator, Programming, Requirements Gathering, etc.


Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.

We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance.

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