Design Verification Engineer - 10213960

  • location: Menlo Park, CA
  • type: Contract
  • salary: $100 - $110 per hour

job description

Design Verification Engineer - 10213960

job summary:
Seeking an experienced Design Verification Engineer to sit with our client, a global leader in Social Networking and Innovative Technology, in Menlo Park, CA. This assignment is one year to start and an ideal candidate must have:

  • 5+ years of proven experience as a DV engineer
  • Hands on experience with SV and UVM
  • Hands on Experience with executable test plans and Coverage Driven verification
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • Familiarity with C/C++
location: MENLO PARK, California
job type: Contract
salary: $100 - 110 per hour
work hours: 8am to 4pm
education: Bachelors

  • Write and augment existing testplans.
  • Implement testbench and scoreboards / checkers.
  • Implement test sequences as per plan and debug failures
  • Achieve 100% functional and code coverage
  • Work closely with designers, micro architects & f/w to resolve issues
  • Ability to communicate & articulate clearly progress / issues with project leads
  • Experience level: Experienced
  • Minimum 5 years of experience
  • Education: Bachelors
  • UVM
  • Engineer
  • Prototype Design
  • Prototypes
  • SystemVerilog
  • Design Verification

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.

We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance.

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