Sr Electrical Engineer - FPGA and ASIC Design Solutions

  • location: Cedar Rapids, IA
  • type: Contract
  • salary: $60 - $70 per hour

job description

Sr Electrical Engineer - FPGA and ASIC Design Solutions

job summary:
  • Become part of the growing FPGA & ASIC Design Solutions team. As an engineer in this organization, you will be a member of an experienced, dynamic design group employing best practice design methodologies supporting our next generation of military GPS products.
  • This position is for an experienced and motivated Senior Electrical or Computer engineering candidate to be involved in the design, implementation, verification and integration of military GPS products.
This position requires these skills and abilities:

  • RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog
  • Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
  • Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGAspecific tools)
  • Familiarity with revision control concepts and tools (e.g. Subversion)
  • Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds
  • strong oral and written communication skills and the ability to document and present one's work and status
  • Bachelor's Degree in applicable engineering field
Desired skills of a successful candidate:

  • Familiarity with best practice chip level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
  • ASIC / FPGA lab validation with advanced lab equipment
  • Design for Test (DFT) and manufacturability issues
  • Experience with Unix, scripting, C/C++, and/or Perl
 
location: Cedar Rapids, Iowa
job type: Contract
salary: $60 - 70 per hour
work hours: 8am to 5pm
education: Bachelors
 
responsibilities:
  • Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration
  • RTL coding and simulation in VHDL or Verilog
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • This position is located in Cedar Rapids, IA.
 
qualifications:
  • Experience level: Experienced
  • Minimum 5 years of experience
  • Education: Bachelors
 
skills:
  • Sr Electrical Engineer
  • FPGA
  • ASIC/FPGA/PLD
  • RTL
  • VHDL
  • Verilog

Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

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