A Senior Analog Design Engineer is needed in the Santa Clara, CA area for an American corporation that supplies equipment, services and software for the manufacture of semiconductor chips for electronics, flat panel displays for computers, smartphones, televisions, and solar products. This senior-level role involves designing, simulating, and verifying complex analog mixed-signal CMOS circuits for semiconductor tools. You will lead the full development lifecycle from negotiating specs and supervising layout to silicon characterization using advanced Cadence tools and analytical problem-solving.
location: Santa Clara, California
job type: Contract
salary: $85.10 - 141.84 per hour
work hours: 8am to 5pm
education: Masters
responsibilities:
- Design and develop mixed-signal integrated circuits for innovative semiconductor fabrication tools.
- Negotiate circuit specifications with internal customers and project stakeholders.
- Translate integrated circuit fabrication process capabilities into functional hardware designs.
- Design, simulate, and verify basic and complex analog and digital CMOS circuits.
- Develop blocks such as bandgap references, low-noise amplifiers, comparators, mixers, and data converters.
- Supervise and review custom analog layouts at both the block and chip levels.
- Design experiments, test boards, and software programs for silicon characterization.
- Troubleshoot and evaluate bench tests during the silicon characterization phase.
- Manage project schedules and tasks to ensure on-time delivery of specifications.
- Lead others in solving complex technical problems using sophisticated analytical thought.
- Communicate difficult technical concepts and influence stakeholders to adopt new viewpoints.
- Utilize Cadence Virtuoso, Spectre, and SystemVerilog for end-to-end IC design and RTL development.
- Analog circuit design experience in DACs, ADCs, current drivers, linear regulators, and other various supporting circuitry in CMOS processes. (high voltage experience is a plus).
- Good understanding of IC device physics, spice models, ESD, latch-up, and manufacturing technology are also required.
- Proficient in the use of Cadence's IC design environment (Virtuoso Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (SystemVerilog).
- Knowledge of mixed mode simulation (Cadence AMS Designer) is a plus.
- Previous experience with testing and characterization of ASICs is very desirable.
- Proficiency in the use of Python to generate test code for silicon verification & characterization.
- Knowledge of lab equipment including digital oscilloscopes, signal generators and Semiconductor Automatic Testers (Advantest/ATE).
- M.S. in Electrical Engineering (or equivalent).
- With at least 5 years of industry experience in design of mixed-signal ASICs.
qualifications:
- Experience level: Experienced
- Education: Masters
skills:
Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.
At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com.
Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility).
This posting is open for thirty (30) days.
Qualified applicants in San Francisco with criminal histories will be considered for employment in accordance with the San Francisco Fair Chance Ordinance.
Qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.
We will consider for employment all qualified Applicants, including those with criminal histories, in a manner consistent with the requirements of applicable state and local laws, including the City of Los Angeles' Fair Chance Initiative for Hiring Ordinance.
