In the development of computer hardware, specifically Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) chips, there are fundamentally four stages of design. Each stage requires specific expertise, tools and flows. They are:

  • requirements/architecture/high-level design
  • implementation (RTL coding aka design entry)
  • verification
  • physical design

At the completion of these steps, an FPGA is programmed, and an ASIC is manufactured. This is a highly simplified description of a very complicated and interactive process. The main skills and functions of verification engineers are the same in ASIC design as in FPGA designs. The software tools used may be different, and the level of rigor may be lower for FPGA designs, since they can often be reprogrammed if a flaw is found in the final programmed hardware.

design verification graph
design verification graph

A verification engineer is tasked with developing software that can simulate, anticipate and detect errors in the design that has been developed by the design engineers. A verification engineer works with the design team to identify design flaws, help resolve problems and verify that the product, service or system will work as expected. Their role is to ensure that the final product meets specifications. This is not the same as saying their role is to ensure the design does what the designer designed. In fact, the role of the verification engineer is to find any and all errors in the design code before the design is physically manufactured, thereby ensuring the highest likelihood of first-pass-silicon. Since FPGAs may be reprogrammed, the verification process can be more iterative than in ASIC design. Finding design flaws in an ASIC after the silicon is produced is very expensive.

Starting with a common set of requirements used by the design team to design a device is a best practice for verification teams. With those requirements, the verification team creates a test plan and implements a verification environment independently of the design team. (When designers are tasked with creating their own verification tests, they have a tendency to create tests that verify what they designed, not what the specification says they should.)

Verification engineers are frequently tasked with creating a multi-level test environment to assess the performance of various system components. The test environment can be typically set up where components receive input and generate output that is analyzed to determine if the output matches the expectations for the given inputs. In essence, a stimulus is generated as input, then the stimulus is pushed through the FPGA or ASIC design, often referred to as the “design under test” (DUT) to a second component. This component, or output collector, takes the DUT’s output information and sends it through a “scoreboard” that verifies that the output is what was anticipated for that input. Because the design DUT is only a concept at this stage, testing requires software capable of simulating actual design performance. The diagram below illustrates the elements and flow of the verification environment.

verification environment graph
verification environment graph

Developing and implementing these testing technologies, as well as analyzing results and proposing remedies to problems, requires technical knowledge in electronic design techniques and computer programming capabilities, as well as training with specific software tools.

which skills should a verification engineer possess?

As is the case with many technology-based jobs, the most successful verification engineers will have a good blend of both hard and soft skills. Although technical skills are mandatory for this type of engineering, these types of product development projects are team-oriented, placing a premium on soft skills as well.

Tech skills required (some will vary depending on the type of development effort):

  • fundamental understanding of digital logic design, clocked logic and event-driven simulation tools
  • ASIC/FPGA verification including directed tests, System Verilog as a language and UVM as a methodology
  • knowledge of design techniques and the most widely used hardware description languages, including Verilog, System Verilog and VHDL
  • experience with simulation and virtual debug tools such as VCS, Modelsim, Questasim, etc.
  • programming experience in such languages as Java, C++, Python, Perl, Bash, TCL, etc.
  • knowledge of design simulation modeling for virtual prototyping environments

Soft skills required:

  • extensive problem-solving capabilities
  • meticulous organization skills that enable multitasking and the ability to move seamlessly between various tasks
  • enthusiastic team player who is good at collaborating
  • solid written and verbal communication skills
  • tenacity to dig deep and find root cause of problems

job roles 

Verification engineers can be involved in a wide range of roles that offer opportunities to apply both hard and soft skills, acquire new knowledge and further your development. Roles might include:

  • meeting with product designers to determine functionality protocols
  • reviewing product design specifications and developing test plans
  • designing verification methodology based on product design specifications
  • determining testing environments and verification tools
  • managing complex tools flows and optimizing software runtimes
  • evaluating third-party verification IP and integrating it into runtime environments
  • planning the method of sequence for testing operations
  • debugging complicated simulation failures in conjunction with design engineers
  • developing constrained random test environments and managing complex metrics for test coverage on high-reliability programs
  • implementing and tweaking testing mechanisms and protocols

how to become a verification engineer?  

In general, verification engineering techniques are not taught in undergraduate engineering programs. At best, a single class in verification may be presented. Most verification engineers transition from design engineers at some point in their career. Training through third-party training companies, attending focused training classes, and mentoring from experienced verification engineers is very common. A CS or EE major with a reasonable training in software, particularly any object-oriented software language, such as C++, will be well suited to learning System Verilog and then a methodology like UVM. A basic understanding of digital clocked logic design is very important for a verification engineer — not so much for writing verification tests, but for debugging the inevitable errors unearthed during verification.

It is recommended that at the university level, courses are taken in digital design, computer architecture, FPGA design (with as much lab experience as possible). In addition, courses in software programming with Python and C++ or equivalent provide a good foundation for transitioning into verification engineering. With background training by employers, third-party training companies or verification-tools vendors, the engineer will find themselves capable of contributing to a verification team right away. More experienced hardware engineers may want to brush up on object-oriented programming before starting on System Verilog for verification.

the job outlook for verification engineers looks bright

Many employers of verification engineers are manufacturers of computer hardware and other electronics products. One measure of those industries’ vibrancy is the anticipated demand for semiconductors. If we use the anticipated demand for semiconductors as a proxy for the health of these industries — and their need for engineering talent — the job outlook is indeed bright. According to the World Semiconductor Trade Statistics’ forecasts, the worldwide semiconductor market is expected to grow by nearly 14 percent in 2022 and 4.6 percent in 2023. IC Insights anticipates an 11 percent increase in semiconductor sales this year, even in the face of the obstacles caused by inflation, higher energy costs and ongoing supply chain bottlenecks.

Verification engineering for digital hardware is highly challenging, collaborative and rewarding. Engineers are in high demand, highly compensated and make a great impact in any business whose success is based on silicon technology!

If a career as a verification engineer sounds like something for you, visit Randstad USA’s job search page to find opportunities near you.

Alternatively, if your company is looking to hire high-impact engineers right now, get in touch with us today to learn how we can help.